The rapid shrinking of gate dimensions of CMOS devices has led the gate line width down to the sub-100 nm regime. For example, the physical line width of the polysilicon gate required for IBM's CMOS 9S technology generation is about 90 nanometers. From a lithography process standpoint, current capabilities with 248 nanometer DUV systems, in conjunction with phase shift mask technology and a single layer resist with thickness of about 450 nanometers, are limited to about 120 nanometers. The resist thickness is limited by the shrinking depth of focus needed to resolve the smaller features. FIG. 1 illustrates the situation, where the post-lithography line width, W0, is about 120 nanometers and the height, H0, is about 450 nanometers. In order to make the gate stack line width smaller than 120 nanometers, a PR trimming step must be used to shrink the lateral dimension, W0. Current technologies use plasmas (containing O2, Ar, etc.) to trim/shrink the dimension of PR masks. The two major limitations of the current technologies are 1) the vertical etch rate of the PR is about three times the lateral etch rate, and 2) the vertical etch rate of the (PR) is about equal the vertical etch rate of the anti-reflective coating (ARC), and is also approximately equal to the etch rate of the hard mask, i.e., the oxide.
The final width and height of the mask stacks, W1 and H1, are determined by W0 and H0 and the vertical and lateral etch rates of the mask and stack. Currently, the smallest line width fabricated by using the PR trim techniques is about 80-90 nanometers. Two known alternatives to achieve smaller dimensions include the use of e-beam direct writing or x-ray lithography. Line widths approximating 50 nanometers can be achieved with e-beam direct writing but the throughput is too slow for mass production. Many challenges have hindered the wide use of x-ray lithography in the IC industry, such as fabrication of the 1X mask, mask materials, mask reliability, overlay correction capabilities and limitations in throughput enhancement capabilities.
Other objects and advantages of the present invention will become apparent from the following disclosure.